This invention relates generally to magnetic data storage devices such as magnetic tape drives and more specifically to the programmable adjustment of equalization in a digital write signal.
Write equalization is commonly used in magnetic storage devices to pre-compensate for distortion in the transmission path of a magnetic data storage device. In magnetic recording, as well as in other communications and transmission-related fields, various forms of optimization and adaptation are applied to transmitted or written data that can improve the ability to recover the original data upon reception or reading. A typical magnetic storage system including a write equalization circuit 10 is shown below in FIG. 1.
Referring now to FIG. 1, input data is received on input data line 12 and pre-distorted by write optimization circuit 14. The output signal of the write optimization circuit is buffered by write buffer 16 and fed to the write head 18. The pre-distorted and buffered input signal is transferred to magnetic tape 20 and read by read head 22, buffered by read buffer 24 and converted to output data on output data line 28 by read circuit 26.
Choosing an appropriate form of optimization is dependent upon a working knowledge of a given recording channel""s many characteristics such as thermal noise, read and write head characteristics, type of media used, and many other factors. These characteristics can all change over time during the course of operation of such systems. If the equalization circuit is static as shown in FIG. 1, and conditions change, system performance will not be optimized until a new write equalization circuit or solution can be implemented.
What is desired, therefore, is the ability to program the write equalization circuitry to accommodate changes in the many characteristics of a magnetic recording system so that various forms of write equalization can be used and system performance can be continually optimized.
According to the present invention, a programmable write equalization circuit includes a first digital clock that is used as a reference to indicate data rate, a second digital clock used to indicate write equalization quantization, a look-up table used to store waveforms used in equalizing the input from the first digital clock domain to the second digital clock domain, a counter used to indicate the number of bits within the look-up table that are to be used for each translation, a polarity detector used to detect the current state of the input data, a non-return-to-zero (NRZ) filter used to indicate the placement of data transitions and non-transitions, and a software interface including programmable registers to control each one of the parameters within the equalization circuit. An integer ratio N relates the first and second clock rates wherein N is also the amount of quantization available to the equalization.
The parameters available to the circuit include the use of NRZ transformation of the data, the variable rate of the first and second clocks, the variable length of the programmable output data sequences, and the actual content of the output data sequences desired. The user of the programmable equalization circuit, who may be a product designer, researcher, or software programmer, can adjust these circuit parameters to attain a desirable output waveform to optimize the ability of a reading circuit to recover the original data after the waveform is transmitted and/or recorded through the media and media access sub-system including the read and write heads, tape medium, and other components shown in FIG. 1.
Desirable optimizations for the equalization circuit of the present invention may include the usage of Schneider write equalization, pulsed writing, pulsed writing with equalization, differential outputs using dual sequence tables, each used as a sequence source for one of the differential lines, differential pulsed waveforms, double-pulsed writing, along with various spacings of the equalization signals. While these are the most typical operations possible with the equalization circuit of the present invention, many variations of output signals are possible enabling the best possible optimization to be implemented, or adapted as needed in real time.
It is an advantage of the equalization circuit of the present invention that it can be entered into manufacturing before any of the storage system operating conditions are known, yet still be optimized once the operating conditions have been precisely specified.
It is an advantage of the present invention that it adds to the flexibility of product development and scheduling.
It is a further advantage of the present invention that the circuit is xe2x80x9cadaptablexe2x80x9d in that it can be continually re-optimized under external control as required by changing conditions in the data storage system.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with references to the accompanying drawings.